The incredible growth in Internet, wireless, and opto-electronic communications has created a need for low-cost, high-performance microsystems, capable of receiving, processing, and transmitting large amounts of data quickly and accurately. However, the increasing use of millimeter-wave and optical channels for communications has made highly integrated, all-silicon communication chips impossible, because of silicon""s ineffectiveness in optical and ultra-high speed applications. Instead, these functions are performed with one of three types of circuits: hybrid circuits, monolithic microwave integrated circuits (MMICs), or opto-electronic integrated circuits (OEICs). Hybrid circuits include separate chips of different materials, such as silicon signal-processing chips and III-V electronic devices to perform optical or microwave functions. These hybrid chips require serial manufacturing techniques, such as pick-and-place and wire-bonding, which increase the cost, size, and complexity of the manufactured circuit. On the other hand, MMICs and OEICs perform not only the optical or microwave function, but also all of their data processing, on the GaAs or InP substrate, which results in inefficient utilization of the expensive III-V material. In order to continue reducing the cost and size of data transmission circuits, a technique for fabricating integrated circuits containing devices made of differing materials must be perfected.
Because of the potential for low-cost, multi-function integrated circuits, heterogeneous integration of silicon and other materials has been explored extensively. The benefits of heterogeneous integration include lower parasitic losses, lower system weight, lower packaging costs, and increased reliability. Ultimately, these benefits will provide reduced cost, higher performance microsystems.
The promise of increased performance has driven research in heterogeneous integration, with numerous unique and creative approaches developed to integrate silicon and III-V devices. These approaches include techniques in which the two different materials are combined early during the process, such as direct growth of III-V materials onto silicon, wafer bonding of silicon and GaAs wafers together, or transferring epitaxial layers onto silicon prior to device processing. Alternately, the III-V devices can be fabricated prior to transfer, and then transferred in processes such as epitaxial lift-off, applique, flip-chip, or fluidic assembly. As described below, each of these processes have potential, but process details limit their use to specific niche applications.
Because silicon and III-V materials are not lattice-matched and have different thermal properties, the growth of device-quality, large-area epitaxial layers on low-cost silicon substrates cannot be performed. However, limited area growth of device-quality III-V material through an opening in a silicon oxide layer has been demonstrated. Operating LEDs and VCSELs have been demonstrated on silicon wafers, and an LED and driver circuit have been integrated using this growth technique. However, devices grown using this technique contain a very high defect density and residual stress, which limits their lifetime. Also, the temperatures required for growth of III-V materials may degrade any existing silicon circuitry.
Wafer bonding has also been proposed, researched and demonstrated for numerous applications. At the device level, InP-InGaAsP lasers were fabricated using direct wafer bonding, while others have demonstrated dual-wavelength emitters by bonding GaN LEDs and InGaP lasers together, and then removing the GaAs substrate. Another wafer-bonding approach that integrates Si circuitry and GaAs devices is known as xe2x80x9cEpitaxy on Electronicsxe2x80x9d. In this approach, a GaAs and SOI wafers are bonded together. The Si wafer is removed, leaving a thin layer of silicon. CMOS devices are fabricated, an opening is etching in the silicon, and GaAs devices can be grown in the opening, processed, and then integrated with the CMOS circuitry. However, wafer bonding requires the use of entire wafers, so it is an inefficient use of the III-V wafer. Also, the thermal cycling required to grow material and fabricate devices generates stress in the bonded wafers, which in extreme cases may result in fracture.
Another unique procedure for heterogeneous integration is epitaxial lift-off (ELO). In this process, epitaxial material is released from the growth substrate by etching a sacrificial layer underneath the epitaxial layer, releasing it from the substrate. The epitaxial layer, typically supported by a wax or polymer membrane, is then bonded to the host substrate through van der Waals bonding. Depending upon the process requirements, the devices can be processed either before or after the transfer of the epitaxial layer to the host substrate. ELO has been reported by several groups for the integration of optical devices with silicon CMOS and for thermal management, but it has three unfortunate drawbacks. First, handling extremely thin epitaxial layers is difficult and tedious. Second, any pre-processed devices need to be aligned to existing circuitry on the host substrate, which is difficult and time-consuming when compounded with the thinness of the epitaxial film. Finally, it inefficiently utilizes material, because the entire epitaxial layer must be consumed in the transfer, regardless of the device density on the final circuit.
Applique can also be used to transfer epitaxial layers to other substrates, either before or after device processing. This procedure differs from ELO in that a surrogate substrate is used to support the epitaxial layers during the transfer step. Also, typically a thin metal solder film, rather than van der Waals forces, is used to attach the epitaxial material to the new substrate. This procedure has been used to fabricate some relatively complex heterogeneous circuits, but still has the problem of inefficient layer transfer. Also, while using a surrogate substrate adds rigidity to the material, it creates the need for a second substrate removal step.
Currently, the most common and successful practice for aligning individual devices is flip-chip mounting. Several complex and high-performance circuits, most notably a high speed optical switching chip with over 4000 modulators, have been demonstrated using this technique. In this process individual die are fabricated, diced from the growth wafers, and mounted upside-down on the host substrate using a pick-and-place tool. Once the devices are held into place by solder bonding, the growth substrate is removed by etching. Because this process involves serial manipulation and alignment of individual device die, it is time consuming and expensive. Additionally, the accuracy obtained with a pick-and-place tool does not allow for fine alignments.
For successful, efficient heterogeneous integration, a process that will align separate discrete die without individual manipulation of the devices is required. There have been two approaches that meet these requirements. These approaches are fluidic self-assembly and vector potential parts manipulation. However, they have there own problems as discussed below.
Fluidic self-assembly is a unique method of assembling many parts in parallel. In this process, carefully etched device die are mated to a substrate with etched holes of matching dimensions. The thick epitaxial devices are lifted-off of the growth substrate, suspended in a liquid solution, and flowed over the host substrate. Driven by gravity and surface forces, the parts align themselves into matching holes in the host substrate. In this process, the alignment tolerance is defined by the etched opening and the shape of the die, rather than by a mechanical alignment. Unfortunately, fluidic self-assembly requires that the device die are made of thick epitaxial layers, which need to be specially shaped to match the openings in the substrate. This requirement is a task that is expensive and difficult to achieve, and typically adds several processing steps, such as ion-milling.
One such fluidic self-assembly is set forth in U.S. Pat. No. 5,824,186 (Smith et al.), U.S. Pat. No. 5,904,545 (Smith et al.), U.S. Pat. No. 5,783,856 (Smith et al.) and U.S. Pat. No. 5,545,291 (Smith et al.), all of which are incorporated herein by reference. The fluidic self-assembly described in the aforementioned patents include a step of transferring the shaped blocks into a fluid to create a slurry. The slurry is then dispensed evenly or circulated over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.
Fluidic self-assembly using either recessed pits or capillary forces provides the advantage of a parallel assembly process with efficient material usage, but relies on xe2x80x9cthe law of large numbersxe2x80x9d to assemble parts, because it is essentially a random process requiring an overabundance of parts for successful assembly. While this works well on dense arrays, it does not offer significant advantages for more sparse arrays of parts.
Another process that allows for the alignment of separate device die is potential-driven assembly. This process uses a potential, most often electrostatic, to direct and place parts. Parts are placed on a vibrating stage and are attracted to potential wells on the substrate. As the vibration is reduced, the parts xe2x80x9cannealxe2x80x9d into place. This is a very promising technique, but it has only been demonstrated with large parts and with extremely high voltages in a specially prepared alignment fixture. U.S. Pat. No. 5,355,577 (Cohn), incorporated herein by reference, discloses one such potential-driven assembly process, wherein devices are placed randomly on a template consisting of a pair of oppositely charged planar electrodes. The upper electrode contains a multiplicity of apertures. The template is vibrated and the devices are attracted to the apertures and trapped therein. The shape of a given aperture determines the number, orientation, and type of device that it traps. The process is completed by mechanically and electrically connecting the devices.
All of these applications, while suitable for specific applications, do not allow for true, versatile heterogeneous integration of three-terminal III-V devices. A process needs to be developed that will be flexible, use epitaxial material efficiently, and place and align devices in parallel.
The present inventors have discovered an unique process electro-fluidic assembly process that is capable of placing and aligning individual electronic devices onto predetermined locations of a substrate, and capable of avoiding the problems with the conventional processes discussed above. The electro-fluidic process according to the present invention is capable of true monolithic integration which allow for the production of designs with low parasitic electrical interconnects and low thermal resistance contact to silicon substrates. In order to improve upon these techniques, we have developed a driven fluidic assembly process called xe2x80x9celectro-fluidic assemblyxe2x80x9d. In this process, device die are suspended in a fluid carrier and aligned to an electrode structure utilizing electric fields. This technique utilizes two effects: dielectrophoresis and electrostatic energy minimization. Dielectrophoresis drives parts over long ranges while electrostatic energy minimization provides short-range alignment. By utilizing these two forces, the present inventors have demonstrated that electronic devices can be drawn to alignment sites and accurately aligned in parallel with a single process step.
Because this process uses directed assembly to position and align parts, it provides faster, more efficient alignments than the essentially random fluidic assembly processes described above. Also, because electric fields and electrohydrodynamic effects are used to physically move the parts, the devices can be any arbitrary shape or material, rather than the carefully machined shapes required by fluidic-self-assembly.
The unique assembly process according to the present invention will enable true heterogeneous, monolithic circuits to be fabricated rapidly, on an arbitrary substrate, with low cost.
The present invention also provides many additional advantages which shall become apparent as described below.
An electro-fluidic assembly process for integration of components, e.g., electronic devices, onto a substrate which comprises: dispensing components within a carrier fluid; attracting the components to an alignment site on the substrate by means of eletrophoresis or dielectrophoresis, which is the motion of a particle in solution when exposed to a electric fields; and aligning the components within the alignment site by means of electrostatic energy minimization, with the alignment site designed such that the ideal alignment position is the component""s preferred alignment.
The carrier fluid is a fluid, such as: water, alcohols, and organic solvents. Examples of components include any electronic, optical, or microelectromechanoical devices fabricated from a combination of electronic materials, such as silicon, germanium, carbon, gallium, indium, aluminum, arsenic, phosphorous, nitrogen, and mixtures thereof. Examples of potential substrate materials include: silicon, ceramic, duroid, and metals.
The substrate comprises: a biased backplane layer, a metal plane layer having an alignment site, a first insulating layer disposed between the backplane layer and the metal plane layer, and a second insulating layer, e.g., a benzocyclobute layer, having a recess disposed therein, wherein the second insulating layer is on the surface of the ground metal plane layer opposite from the first insulating layer and wherein the recess is in communication with the alignment site.
The means of dielectrophoresis comprises the application of an electric field between the backplane layer and the metal plane layer, wherein the electric field is in the range between about 1 V/cm to 1010 V/cm.
The present invention further comprises a substrate for use in electro-fluidic assembly, wherein the substrate comprises: a biased backplane layer, a metal plane layer having one or more alignment sites, an first insulating layer disposed between the backplane layer and the metal plane layer, and an upper insulating layer having a recess disposed therein, wherein the second insulating layer is on the surface of the metal plane layer opposite from the first insulating layer and wherein the recess is in communication with the alignment site.
The biased backplane layer is form from at least one material selected from the group consisting of: doped semiconductor, metals, and conducting polymers. The metal layer formed from at least one material selected from the group consisting of: gold, gold, aluminum, palladium, titanium, copper, platinum, tantalum, doped semiconductor. The insulating layer at least one material selected from the group consisting of: SiO2, Si3N4, glass, polymers, and vacuum.
Other and further objects, advantages and features of the present invention will be understood by reference to the following specification in conjunction with the annexed drawings, wherein like parts have been given like numbers.